测试、测量和监测仪器提供商泰克公司日前宣布， PulseCore半导体已经成功地采用泰克全套测试仪器，测试和验证其最新推出的USB 2.0集成电路(IC)。新推出的PulseCore IC在业内率先采用扩频时钟(SSC)降低电磁干扰(EMI)，同时满足了USB 2.0行业标准。
为测量是否满足USB 2.0行业标准和信号完整性，PulseCore结合使用装有TDSUSB2软件选项的DPO7254示波器、TDSUSBF测试夹具和P7360A 6 GHz差分有源探头。为测量电缆上的及辐射的USB 2.0 EMI功率降低情况，PulseCore还使用了带有DPX实时RF显示技术的RSA6114A实时频谱分析仪(RTSA)。DPX波形图像处理技术可以提供频谱的实时RF信息，揭示以前看不到的RF信号和信号异常事件。
“泰克是USB设计和一致性测试的领导者。”PulseCore工程设计总监Dan Hariton说，“我们面临着一个特别困难的测试挑战，需要验证USB 2.0标准满足情况及EMI降低情况，因此我们转向专家求助。泰克测试套件自动进行测量检定和报告采集工作，同时消除了耗时的手动设置工作，为我们节约了大量的时间。”
通过使用这一测试套件，PulseCore能够验证其SSC技术的效果，该技术的平均EMI衰减为4dB，满足了USB 2.0标准。RTSA在跳变中和跳变后实时分析SSC，保证示波器检验、调试和测试设计时，关键SSC参数一直满足规范。
仪器和软件的速度、可重复性和灵活性提供了额外的优势，帮助PulseCore找到新型IC的极限，最终为PulseCore客户提供更多的设计选项。借助PuseCore详细测试发现的信息，使用新型IC的系统设计人员可以了解极限特点，优化设计，实现最大性能，或最大限度地降低EMI。
“泰克设备和软件自动进行设置和一致性测试，在设计阶段和验证阶段为我们节约了大量的时间。如果没有这些设备和软件，我们不可能把我们的芯片推向极限。”Hariton接着说。
2008年10月16日星期四
2008年10月14日星期二
安捷伦U1253A使用最新的有机发光显示管（OLED）
Agilent Technologies Inc. has introduced the U1253A handheld digital multimeter (DMM), touting it as the first DMM to use an organic light-emitting diode (OLED) display.
For on-the-go and benchtop applications, the OLED readout provides a 2000:1 contrast ratio, a 160-degree viewing angle, smoothed fonts and a "large display" mode to ensure crystal-clear indoor viewing.
Designed to simplify electronic troubleshooting and validation, these high-performance instruments enable engineers and technicians to complete their day-to-day tasks without being confined to the bench.
All three U1250 Series DMMs provide useful benefits that help simplify analysis, accelerate glitch detection and simplify probing of hard-to-reach points.
Key specifications are 4.5-digit resolution with 50,000-count full-scale dual display and basic accuracy of up to 0.025 percent. All offer simultaneous measurements and provide the flexibility to quickly perform validation tests, tolerance checks and marginal-failure troubleshooting.
Pricing: $449.Availability: Now worldwide.Datasheet: Click here.
For on-the-go and benchtop applications, the OLED readout provides a 2000:1 contrast ratio, a 160-degree viewing angle, smoothed fonts and a "large display" mode to ensure crystal-clear indoor viewing.
Designed to simplify electronic troubleshooting and validation, these high-performance instruments enable engineers and technicians to complete their day-to-day tasks without being confined to the bench.
All three U1250 Series DMMs provide useful benefits that help simplify analysis, accelerate glitch detection and simplify probing of hard-to-reach points.
Key specifications are 4.5-digit resolution with 50,000-count full-scale dual display and basic accuracy of up to 0.025 percent. All offer simultaneous measurements and provide the flexibility to quickly perform validation tests, tolerance checks and marginal-failure troubleshooting.
Pricing: $449.Availability: Now worldwide.Datasheet: Click here.
安捷伦发布针对MIMO接收机测试的实验室仪器
编辑笔记：安捷伦发布的这款针对MIMO接收机测试仪器可升级，同时也具有更高的速度和更好的精度。安捷伦声称这是目前市场上能够模拟真实通信环境的最好产品。该产品支持2*2，2*4，4*2路MIMO测试。该产品的售价为31000美金。
Agilent Technologies has announced a scalable laboratory instrument that enables quicker, more accurate testing of MIMO (multiple-input/multiple-output) receivers earlier in the design cycle. Providing what the company calls the market’s best simulation of real-world conditions, the new N5106A PXB MIMO-receiver tester, enables significant reductions in the time to develop and qualify new products. By minimizing design uncertainty and setup time and providing the performance and scalability to meet future test needs, the instrument transforms MIMO test, according to Agilent. Its capabilities make the new tester ideal for R&D engineers who develop and integrate MIMO receivers for 3GPP (third-generation-partnership-project), LTE (long-term-evolution), WiMax (worldwide-interoperability-for-microwave-access), and emerging wireless standards.
The tester provides versatile signal-creation and channel-emulation for the latest LTE and WiMax standards. It supports 2×2 (two-transmitter/two-receiver), 2×4 (two-transmitter/four-receiver), and 4×2 (four-transmitter/two-receiver) MIMO with 120-MHz bandwidth and features custom MIMO-correlation settings—for example, channel models, antenna pattern, and correlation matrix. Signal Studio signal-creation software runs in the instrument and provides up-to-date standards-compliant signal creation.
Using the PXB, you can simulate real-world conditions in the lab to more quickly test corner cases and stress devices beyond standards requirements. You can also test coexistence to ensure design robustness earlier in the design process. Using Signal Studio, Advanced Design System software, or even a waveform-creation tool that you wrote yourself, you can sum the outputs of as many as four high-performance baseband generators to perform multiformat coexistence testing. Each baseband generator supports 120-MHz modulation bandwidth with 512M samples of playback memory for simulating long, complex signals. This approach enables earlier identification of problems, which allows you to design with greater confidence and thereby reduce uncertainties, minimize rework, and shorten time to market.
Seamless signal routing and automated power calibration minimize test time and eliminate the time-consuming system setup previously required for fading and multiformat coexistence-signal summing. Predefined test configurations further reduce test time and allow you to quickly define complex instrument settings. A GUI (graphical user interface) with drop-down menus speeds learning and provides quick selection of test settings such as MIMO-channel models and path configurations.
The tester features a scalable, high-performance platform based on a field-upgradable architecture. Adding support for the test needs of future technologies, such as 4G (fourth-generation) and higher-order MIMO implementations, requires only a cost-effective upgrade that you can perform in an hour. The architecture extends the instrument’s service life, maximizes your equipment investments, and reduces the cost of test by allowing you to use existing Agilent signal generators and analyzers and other RF-test equipment. Pricing depends on the system configuration and begins at $31,000.
Agilent Technologies has announced a scalable laboratory instrument that enables quicker, more accurate testing of MIMO (multiple-input/multiple-output) receivers earlier in the design cycle. Providing what the company calls the market’s best simulation of real-world conditions, the new N5106A PXB MIMO-receiver tester, enables significant reductions in the time to develop and qualify new products. By minimizing design uncertainty and setup time and providing the performance and scalability to meet future test needs, the instrument transforms MIMO test, according to Agilent. Its capabilities make the new tester ideal for R&D engineers who develop and integrate MIMO receivers for 3GPP (third-generation-partnership-project), LTE (long-term-evolution), WiMax (worldwide-interoperability-for-microwave-access), and emerging wireless standards.
The tester provides versatile signal-creation and channel-emulation for the latest LTE and WiMax standards. It supports 2×2 (two-transmitter/two-receiver), 2×4 (two-transmitter/four-receiver), and 4×2 (four-transmitter/two-receiver) MIMO with 120-MHz bandwidth and features custom MIMO-correlation settings—for example, channel models, antenna pattern, and correlation matrix. Signal Studio signal-creation software runs in the instrument and provides up-to-date standards-compliant signal creation.
Using the PXB, you can simulate real-world conditions in the lab to more quickly test corner cases and stress devices beyond standards requirements. You can also test coexistence to ensure design robustness earlier in the design process. Using Signal Studio, Advanced Design System software, or even a waveform-creation tool that you wrote yourself, you can sum the outputs of as many as four high-performance baseband generators to perform multiformat coexistence testing. Each baseband generator supports 120-MHz modulation bandwidth with 512M samples of playback memory for simulating long, complex signals. This approach enables earlier identification of problems, which allows you to design with greater confidence and thereby reduce uncertainties, minimize rework, and shorten time to market.
Seamless signal routing and automated power calibration minimize test time and eliminate the time-consuming system setup previously required for fading and multiformat coexistence-signal summing. Predefined test configurations further reduce test time and allow you to quickly define complex instrument settings. A GUI (graphical user interface) with drop-down menus speeds learning and provides quick selection of test settings such as MIMO-channel models and path configurations.
The tester features a scalable, high-performance platform based on a field-upgradable architecture. Adding support for the test needs of future technologies, such as 4G (fourth-generation) and higher-order MIMO implementations, requires only a cost-effective upgrade that you can perform in an hour. The architecture extends the instrument’s service life, maximizes your equipment investments, and reduces the cost of test by allowing you to use existing Agilent signal generators and analyzers and other RF-test equipment. Pricing depends on the system configuration and begins at $31,000.
ATE厂商前景黯淡？
编辑笔记：ATE行业的衰退已经结束，还是没有？在最近的西部半导体贸易展上，传闻日本横河电气集团将要发布自己的ATE产品线。横河也是工业自动化行业，仪器以及其他产品的的供应商，但是这些产品线显然不是为此次贸易展准备的。
The shakeout in the automatic test equipment (ATE) business is over. Or is it?
At the Semicon West Trade Show, there were rumors that Japan's Yokogawa Electric Corp. may put its semiconductor ATE business on the block. Yokogawa also sells industrial automation equipment, instruments and other products, but those lines are apparently not for sale, according to sources.
The company has a strong presence in Asia, but the company has been nearly invisible in the U.S. market, according to analysts. For its fiscal year, the company's test and measurement group posted an operating loss of 1.9 billion yen ($17.8 million) on sales of 67.8 billion yen ($635 million). This compares to operating profit of 1.1 billion yen ($10.3 million) on sales of 78.5 billion yen ($735.2 million) the previous year.
The Japanese company dismissed the rumor. "We have no plan at present to divest our ATE business," according to a spokesman from Yokogawa, in an e-mail.
"As you know, market conditions at present are tough. Hence, what we are struggling for in our ATE business is to establish a business structure that can be profitable regardless of what happens in the business environment," the spokesman said. "In this regard, we are implementing a selection and concentration strategy. However, it does not mean that we will divest the ATE business," he added.
Anticipated lossIn any case, it's been a tough cycle for ATE vendors. Many suppliers failed to recover in the last downturn in 2001. Now they face yet another downturn, as the ATE segment is expected to decline by 20.3 percent in 2008, according to Gartner Inc.
"It's a tough business," said Rod Stewart, general manager, SOC business group, Teradyne Inc., in an interview at Semicon West. "The outlook is not terribly strong for the 2H of the year," he added.
The net result is more consolidation. The long-awaited consolidation finally hit the ATE market late last year, as Teradyne reentered the flash-memory test business by buying Nextest Systems Corp. for $325 million.
Late last year, Verigy Inc., the ATE spin-off of Agilent Technologies Inc., signed a definitive agreement to acquire DFM chip test vendor Inovys Corp.
Continuing to divest its unwanted lines, Credence Systems Corp. in June entered into a definitive agreement to sell its automotive ATE unit in Amerang, Germany to Advantest Corp. for $5 million. Last month, ATE gear rivals Credence and LTX Corp. said they are planning to merge in an all-stock merger of equals.
ATE rivalsThe shakeout leaves the following competitors in ATE: Advantest, Eagle Test Systems, LTX-Credence, Teradyne, Verigy, Yokogawa and perhaps a few niche players.
For years, analysts insisted there were too many ATE players going after a nongrowth market. Many believe there are still too many vendors. So expect another wave of merger and acquisition activity.
"There needs to be more consolidation," Stewart said. "I would not be surprised to see more of it."
"Over time, there is room for only three or four major players in ATE," said Greg Smith, general manager, broadband and computing business unit, Teradyne.
So which company is next in the ATE shakeout? Some question the viability of the LTX-Credence duo. Both are relatively weak players that even struggled during the upturn. LTX's management appears to have the upperhand in the LTX-Credence merger hierarchy. There is also product overlap between the two companies, leaving many to wonder about the fate of Credence's Sapphire and other ATE lines.
Because of this, the LTX-Credence duo will most likely become a niche player over time. Eagle is also a niche player, but the vendor has confounded critics and rivals, as it has found a way to make a profit in the ATE downturn.
Search for a partnerTo save face, Yokogawa will mostly likely find an ATE partner over time. Some wonder if Advantest Corp. will assume control over that company's ATE business in the future.
This leaves the ATE industry with three big players such as Advantest, Teradyne and Verigy. At one time, it was widely believed that Advantest would trounce its rivals and would become the undisputed champion in ATE.
But even mighty Advantest is struggling. Its memory ATE business is flat on its back amid the downturn in DRAMs and flash. And its SoC test unit, which was riding high at one juncture, has fallen on hard times.
Advantest's logic test business exploded in recent times, thanks to the T2000 line of testers. Intel Corp. procured a plethora of these testers in the early part of the decade, but that business has dried up at the chip giant.
Verigy and Teradyne have each fared relatively well in logic test, but the hated ATE rivals face some major challenges in NAND ATE. The downturn in NAND presents some major economic challenges for Advantest, Teradyne and Verigy, leaving some to believe there is only room for two NAND flash memory test vendors.
Quest for survivalAdvantest will most likely protect its base in the DRAM and flash ATE categories. The question is which company between Teradyne and Verigy is stronger and will survive in NAND ATE.
In logic test, there are some hits and misses in the market, but wireless is especially strong. There is a sea of change in wireless design, as vendors have integrated significant functions on the same device.
"We are thankful to the wireless trends, the 1H was good for us," said Stewart. "Wireless is the dominating driver for us," he added.
To prepare for the next cycle, it has introduced five new products in the past five months. Introductions include the UltraWave 12G wireless test instrument; the high density UltraPin800 instrument; the small footprint UltraFLEX-HD test system; the D750Ex LCD driver test system; and the Magnum II memory test system for flash and embedded memory.
- Mark LaPedusEE Times
The shakeout in the automatic test equipment (ATE) business is over. Or is it?
At the Semicon West Trade Show, there were rumors that Japan's Yokogawa Electric Corp. may put its semiconductor ATE business on the block. Yokogawa also sells industrial automation equipment, instruments and other products, but those lines are apparently not for sale, according to sources.
The company has a strong presence in Asia, but the company has been nearly invisible in the U.S. market, according to analysts. For its fiscal year, the company's test and measurement group posted an operating loss of 1.9 billion yen ($17.8 million) on sales of 67.8 billion yen ($635 million). This compares to operating profit of 1.1 billion yen ($10.3 million) on sales of 78.5 billion yen ($735.2 million) the previous year.
The Japanese company dismissed the rumor. "We have no plan at present to divest our ATE business," according to a spokesman from Yokogawa, in an e-mail.
"As you know, market conditions at present are tough. Hence, what we are struggling for in our ATE business is to establish a business structure that can be profitable regardless of what happens in the business environment," the spokesman said. "In this regard, we are implementing a selection and concentration strategy. However, it does not mean that we will divest the ATE business," he added.
Anticipated lossIn any case, it's been a tough cycle for ATE vendors. Many suppliers failed to recover in the last downturn in 2001. Now they face yet another downturn, as the ATE segment is expected to decline by 20.3 percent in 2008, according to Gartner Inc.
"It's a tough business," said Rod Stewart, general manager, SOC business group, Teradyne Inc., in an interview at Semicon West. "The outlook is not terribly strong for the 2H of the year," he added.
The net result is more consolidation. The long-awaited consolidation finally hit the ATE market late last year, as Teradyne reentered the flash-memory test business by buying Nextest Systems Corp. for $325 million.
Late last year, Verigy Inc., the ATE spin-off of Agilent Technologies Inc., signed a definitive agreement to acquire DFM chip test vendor Inovys Corp.
Continuing to divest its unwanted lines, Credence Systems Corp. in June entered into a definitive agreement to sell its automotive ATE unit in Amerang, Germany to Advantest Corp. for $5 million. Last month, ATE gear rivals Credence and LTX Corp. said they are planning to merge in an all-stock merger of equals.
ATE rivalsThe shakeout leaves the following competitors in ATE: Advantest, Eagle Test Systems, LTX-Credence, Teradyne, Verigy, Yokogawa and perhaps a few niche players.
For years, analysts insisted there were too many ATE players going after a nongrowth market. Many believe there are still too many vendors. So expect another wave of merger and acquisition activity.
"There needs to be more consolidation," Stewart said. "I would not be surprised to see more of it."
"Over time, there is room for only three or four major players in ATE," said Greg Smith, general manager, broadband and computing business unit, Teradyne.
So which company is next in the ATE shakeout? Some question the viability of the LTX-Credence duo. Both are relatively weak players that even struggled during the upturn. LTX's management appears to have the upperhand in the LTX-Credence merger hierarchy. There is also product overlap between the two companies, leaving many to wonder about the fate of Credence's Sapphire and other ATE lines.
Because of this, the LTX-Credence duo will most likely become a niche player over time. Eagle is also a niche player, but the vendor has confounded critics and rivals, as it has found a way to make a profit in the ATE downturn.
Search for a partnerTo save face, Yokogawa will mostly likely find an ATE partner over time. Some wonder if Advantest Corp. will assume control over that company's ATE business in the future.
This leaves the ATE industry with three big players such as Advantest, Teradyne and Verigy. At one time, it was widely believed that Advantest would trounce its rivals and would become the undisputed champion in ATE.
But even mighty Advantest is struggling. Its memory ATE business is flat on its back amid the downturn in DRAMs and flash. And its SoC test unit, which was riding high at one juncture, has fallen on hard times.
Advantest's logic test business exploded in recent times, thanks to the T2000 line of testers. Intel Corp. procured a plethora of these testers in the early part of the decade, but that business has dried up at the chip giant.
Verigy and Teradyne have each fared relatively well in logic test, but the hated ATE rivals face some major challenges in NAND ATE. The downturn in NAND presents some major economic challenges for Advantest, Teradyne and Verigy, leaving some to believe there is only room for two NAND flash memory test vendors.
Quest for survivalAdvantest will most likely protect its base in the DRAM and flash ATE categories. The question is which company between Teradyne and Verigy is stronger and will survive in NAND ATE.
In logic test, there are some hits and misses in the market, but wireless is especially strong. There is a sea of change in wireless design, as vendors have integrated significant functions on the same device.
"We are thankful to the wireless trends, the 1H was good for us," said Stewart. "Wireless is the dominating driver for us," he added.
To prepare for the next cycle, it has introduced five new products in the past five months. Introductions include the UltraWave 12G wireless test instrument; the high density UltraPin800 instrument; the small footprint UltraFLEX-HD test system; the D750Ex LCD driver test system; and the Magnum II memory test system for flash and embedded memory.
- Mark LaPedusEE Times
USB3.0来了
编辑笔记：
USB flash drives such as the Kanguru FlashBlu now hold up to 64 Gbytes of data. Courtesy of Kanguru.With 64-Gbyte flash drives and terabyte external hard drives now available, USB 2.0 has become a data bottleneck. USB 3.0, with its 5-Gbps bit rate, will change that. If you plan to develop USB 3.0 products and you’re not currently testing other high-speed buses such as PCIe (PCI Express) Gen2 or SATA-3 (Serial ATA III), start making a case to your manager for a faster oscilloscope.
USB 3.0 will leverage technology from PCIe Gen2 (5-Gbps) and SATA-3 (6-Gbps) serial buses. It will use 8b/10b data encoding, which reduces the data throughput rate to a maximum of 4 Gbps. “In practice,” said Mike Engbretson, USB test solution marketing manager at Tektronix, “the data throughput may be around 3 Gbps.” Still, the 5-Gbps bit rate is more than 10X faster than USB 2.0. (Click here to read a discussion with Engbretson, covering USB 3.0 technology in more detail.)
Like PCIe Gen2, USB 3.0 will use a 2.5-GHz fundamental clock frequency. So, you’ll likely need a 12.5-GHz oscilloscope if you need to see a signal’s fifth harmonic. USB 3.0 will also require you to measure a signal at the receiver, which isn’t necessary for USB 2.0. With the higher bit rate, USB 3.0 receivers will need equalization at the receiver because the signal eye will be closed after traveling through PCB traces, connectors, and cables.
Just how much oscilloscope bandwidth you’ll need is still open to debate. Jim Choate, product management engineer at Agilent Technologies, suggests that using a 10-GHz oscilloscope at the receiver will reduce the amount of jitter and noise you’ll see because some noise is generated by the instrument itself. “There’s very little high-frequency content at the receiver,” he said.
Engbretson countered that you’ll need 12.5 GHz to capture the signal’s fifth harmonic and that using a lower-bandwidth oscilloscope will reduce the amplitude of the measured signal. Engbretson, Choate, and Mike Micheletti, senior product marketing manager at LeCroy, agree that you’ll need to use a 12.5-GHz oscilloscope at the transmitter.
Sample rate will be equally important because of the USB 3.0 signal’s rise time. “At the transmitter,” noted Choate, “edges will rise in less than 70 ps.” You’ll need a sample rate fast enough to measure the signal’s rise time.
“The USB 3.0 specification could specify a 50-ps minimum rise time, although actual hardware may not reach that speed,” said Steven Sanders, product development engineer at LeCroy.
USB 3.0 should have a specification version 1.0 in time for a USB developer’s conference in November. Initial USB 3.0 interface ICs and consumer products should appear in mid-2009, with widespread deployment in 2010. You can expect the first USB 3.0 products to be data-storage devices such as flash drives, external hard drives, digital music players, and digital cameras. After that will come video products and, eventually, data-acquisition systems that need the high data throughput.
------------------------------------------------------------------------------------------------
Programmable power supplies
Lambda’s NV-350 and NV-700 series programmable power supplies provide up to 350-W and up to 700-W continuous output, respectively. Both series are 1U high and operate from 90 VAC to 264 VAC. Outputs are 3.2 V–3.6 V at 40 A and range up to 24 V–26.4 V at 25 A. www.lambdapower.com/products/nv-series.htm.
Oscilloscope consulting service
Amherst Systems Associates (ASA), maker of M1 oscilloscope software, has started a consulting service to help you choose an oscilloscope. ASA’s ScopeMatch program can keep you from buying more oscilloscope than necessary. ASA will discuss signals, probing, software, and oscilloscope specifications with you. www.amherst-systems.com/scope-match.htm.
Instrument software for PC sound card
FreeView-Sound-Pro from Hacker Technology turns your PC sound card into a datalogger, chart recorder, oscilloscope, or FFT analyzer. With an eight-channel sound card, the software can operate on all eight channels at the full speed and resolution of the card. It can store data files up to 2 Gbytes and operates with Windows 95 through Vista. www.hacker-technology.com/100493.html.
Programmable power supplies
Lambda’s NV-350 and NV-700 series programmable power supplies provide up to 350-W and up to 700-W continuous output, respectively. Both series are 1U high and operate from 90 VAC to 264 VAC. Outputs are 3.2 V–3.6 V at 40 A and range up to 24 V–26.4 V at 25 A. www.lambdapower.com/products/nv-series.htm.
Oscilloscope consulting service
Amherst Systems Associates (ASA), maker of M1 oscilloscope software, has started a consulting service to help you choose an oscilloscope. ASA’s ScopeMatch program can keep you from buying more oscilloscope than necessary. ASA will discuss signals, probing, software, and oscilloscope specifications with you. www.amherst-systems.com/scope-match.htm.
Instrument software for PC sound card
FreeView-Sound-Pro from Hacker Technology turns your PC sound card into a datalogger, chart recorder, oscilloscope, or FFT analyzer. With an eight-channel sound card, the software can operate on all eight channels at the full speed and resolution of the card. It can store data files up to 2 Gbytes and operates with Windows 95 through Vista. www.hacker-technology.com/100493.html.
测试金点子：用串行端口控制ADC
编辑笔记：工程师通常需要一个与PC链接的简单测量电路。如果你没有能力去买一个低速的数字化仪，那么你可以自己用两个连接到PC串行端口的IC做一个数字化仪。数字化仪的吞吐率主要取决于操作系统的性能，处理器速度，以及内存。文中作者能在2.4G奔腾处理器，512M内存，WinXP操作系统配置的PC上做到250Sa/s。高速处理器也就意味着高采样率。通过计算一秒钟内转换的二进制数，你就能够计算出你的吞吐率。
Engineers often need simple measurement circuits that connect to a PC. When you don't have the resources to buy a digitizer for low-speed signals, you can build one yourself with just two ICs connected to a PC's serial port. The throughput rate of the digitizer depends mainly on the performance of the PC's operating system, processor speed, and memory. I was able to achieve 250 samples/s with a 2.4-GHz Pentium-based PC with 512 Mbytes RAM running Windows XP. Faster processors will produce higher sample rates. You can calculate your throughput rate by counting the number of conversions for 1 s.
Do you have a test or design idea you'd like to share? Publish it here and receive $150. Send us your ideas.
The circuit in Figure 1 shows that you can use an MCP3201 12-bit successive-approximation ADC (analog-to-digital converter) with a MAX232 RS-232 interface IC. Using an application written in C#, you can get data into a PC that runs Windows XP or Vista. (Click to download the source code.)
Figure 1. A MAX232 IC interfaces an MCP3201 ADC to a PC’s serial port.The MCP3201 uses RTS (ready-to-send), CTS (clear-to-send), and DTR (data-terminal ready) serial-port lines to communicate with a PC. Its standard SPI (serial peripheral interface) port communicates to the MAX232. The analog signal connects to the MCP3201's IN+ pin, and the MAX232 converts RS-232 signal levels to TTL-compatible levels.
The digital output stream from the DOUT pin goes through the MAX232 to the serial point on the IC's CTS line. The RTS line provides clock pulses to the ADC's CLK (clock) pin. Each separate bit appears at the DOUT pin on the falling edge of the CLK signal. Thus, a software application must latch the bit on the rising edge of the clock pulse. Finally, the DTR line produces the CS (chip select) signal that frames the conversion process. The CS bit must be low while the conversion is in progress. Figure 2 shows a timing diagram of the process.
Figure 2. Software latches 15 bits, discarding the first three after reading the data.In Figure 2, the valid data bits (most-significant bit first) appear on the DOUT line after the third CLK pulse goes low. Thus, you must use software to discard the first three bits after reading the data.
The software application is written in free MicrosoftVisual C# 2008 Express Edition. The built-in SerialPort component in C# provides full control over the port. The software is implemented as a simple console application. You don't need a device driver to use a serial port with this code.
You can easily repeat or modify the source code to fit your application. For example, you can send the data from the ADC to another location over the Internet or pass data to Excel or another application for analysis.
You can also improve on the hardware design in Figure 1. For example, placing a low-pass filter in front of the ADC will reduce noise and thus reduce errors caused by aliasing. Always use a bypass capacitor on the MAX232's VCC pin. Place the 1-μF capacitor (recommended value) as close as possible to the device pin.
You can replace the MCP3201 with a similar successive-approximation ADC that also has an SPI-compatible interface. For instance, you may use a Linear Technology LTC1286 or LTC1297. If you plan to use a different ADC, you will need to make some hardware modifications, so check the manufacturer's data sheet for details. Instead of a MAX232 line driver, you can use similar parts such as MAX225 or MAX233. These parts don't require any external components, thus simplifying the design.
If you use other hardware, you may need to modify the application source code, too. As an example, you may need to change the for (int i = 0; i < 15; i++) loop statement in the source code according to the timing diagram of the part you select.
Engineers often need simple measurement circuits that connect to a PC. When you don't have the resources to buy a digitizer for low-speed signals, you can build one yourself with just two ICs connected to a PC's serial port. The throughput rate of the digitizer depends mainly on the performance of the PC's operating system, processor speed, and memory. I was able to achieve 250 samples/s with a 2.4-GHz Pentium-based PC with 512 Mbytes RAM running Windows XP. Faster processors will produce higher sample rates. You can calculate your throughput rate by counting the number of conversions for 1 s.
Do you have a test or design idea you'd like to share? Publish it here and receive $150. Send us your ideas.
The circuit in Figure 1 shows that you can use an MCP3201 12-bit successive-approximation ADC (analog-to-digital converter) with a MAX232 RS-232 interface IC. Using an application written in C#, you can get data into a PC that runs Windows XP or Vista. (Click to download the source code.)
Figure 1. A MAX232 IC interfaces an MCP3201 ADC to a PC’s serial port.The MCP3201 uses RTS (ready-to-send), CTS (clear-to-send), and DTR (data-terminal ready) serial-port lines to communicate with a PC. Its standard SPI (serial peripheral interface) port communicates to the MAX232. The analog signal connects to the MCP3201's IN+ pin, and the MAX232 converts RS-232 signal levels to TTL-compatible levels.
The digital output stream from the DOUT pin goes through the MAX232 to the serial point on the IC's CTS line. The RTS line provides clock pulses to the ADC's CLK (clock) pin. Each separate bit appears at the DOUT pin on the falling edge of the CLK signal. Thus, a software application must latch the bit on the rising edge of the clock pulse. Finally, the DTR line produces the CS (chip select) signal that frames the conversion process. The CS bit must be low while the conversion is in progress. Figure 2 shows a timing diagram of the process.
Figure 2. Software latches 15 bits, discarding the first three after reading the data.In Figure 2, the valid data bits (most-significant bit first) appear on the DOUT line after the third CLK pulse goes low. Thus, you must use software to discard the first three bits after reading the data.
The software application is written in free MicrosoftVisual C# 2008 Express Edition. The built-in SerialPort component in C# provides full control over the port. The software is implemented as a simple console application. You don't need a device driver to use a serial port with this code.
You can easily repeat or modify the source code to fit your application. For example, you can send the data from the ADC to another location over the Internet or pass data to Excel or another application for analysis.
You can also improve on the hardware design in Figure 1. For example, placing a low-pass filter in front of the ADC will reduce noise and thus reduce errors caused by aliasing. Always use a bypass capacitor on the MAX232's VCC pin. Place the 1-μF capacitor (recommended value) as close as possible to the device pin.
You can replace the MCP3201 with a similar successive-approximation ADC that also has an SPI-compatible interface. For instance, you may use a Linear Technology LTC1286 or LTC1297. If you plan to use a different ADC, you will need to make some hardware modifications, so check the manufacturer's data sheet for details. Instead of a MAX232 line driver, you can use similar parts such as MAX225 or MAX233. These parts don't require any external components, thus simplifying the design.
If you use other hardware, you may need to modify the application source code, too. As an example, you may need to change the for (int i = 0; i < 15; i++) loop statement in the source code according to the timing diagram of the part you select.
与模拟测试一样，功率监控测试成为一大看点
编辑笔记：功率监控测试是今年ITC上的一个重要话题。
Power-aware test will be the focus of a panel discussion and two technical paper sessions and is a key topic at this year’s International Test Conference, says Nur Touba, Professor, Department of Electrical and Computer Engineering, University of Texas at Austin, and Program Chair of this year’s ITC. The conference and associated Test Week presentations, to be held October 26-31 in Santa Clara, CA, will also focus on other hot topics, Touba says, such as analog test, which will be addressed in an interactive talk with analog legend Bob Pease. Events of note include a new poster session, a panel on university DFT implementations and a new workshop on design for reliability and variability. Touba discussed this year’s ITC in a phone interview.
The theme of last year’s conference was “facing nanometer test challenges.” What’s this year’s theme?
The steering committee decided not to have a theme this year. The thinking was it really wasn’t driving the program a lot beyond possibly the selection of the keynote speaker.
Who is the keynote speaker this year?
Mike Lydon, VP of test and quality at Cisco, will deliver the keynote address, which is titled “Managing Test in the End-to-End, Mega Supply Chain.” He’s going to talk about managing the supply chain and using test to make real-time end-to-end adjustments over the product’s lifecycle.
Will you have invited addresses?
Yes, we have three invited talks. Just like last year, they will be after lunch each of the three days of the conference.
In the first one, “Computing at the Crossroads (and What Does it Mean to Verification and Test?),” Jan Rabaey of the University of California, Berkeley, will talk about how technology scaling, distributed computation, and physical models of computing will all have a profound effect on how we verify and test designs in the future.
The second talk—“Having FUN with Analog Test—will be given by Bob Pease, staff scientist at National Semiconductor and a legend in the analog community with 48 years of experience. He’s going to be having an interactive conversation—answering questions from the audience—which is something new for an ITC invited address.
Third talk will be given by Jeff Rearick, AMD Fellow, who will talk about how to tell if DFT and test are adding value to your company and how to justify your investment in test.
What are the program highlights this year?
We have added several new features to the program. One is a poster session, which differs from what some conferences do. Some conferences invite regular paper submissions that don’t make the cut to be presented as posters. What we’ve done is have a totally separate submission and review process for the posters. The thinking is, there are some people out there who have some really interesting data, but they don’t have time to write up a 10-page paper about it. The poster submissions require only a one-page summary, so it makes it easy for busy people to come and present their data.
Also, while the regular paper submission deadline was in February, the poster submission deadline was in July, which allows people to submit more late-breaking results. And by presenting a poster, they can get some feedback that helps them write a full paper for the next ITC. In addition, with the poster session we encouraged people to submit on nontraditional topics that wouldn’t necessarily be appropriate as research papers.
When is the poster session?
After the Wednesday afternoon panels last year we held a wine and cheese party. This year on Wednesday we are having an Oktoberfest party, and it’s during that party that the 27 posters will be presented. The presenters will have laptops available to show demos.
What about tutorials?
Another new feature we have this year is embedded tutorials. Of course we will have the 17 tutorials on Sunday and Monday, like we’ve had in the past, but the embedded tutorials will take place on Tuesday morning, during the conference itself. They are included with your registration—you don’t have to pay extra for them. One on mixed-signal production test will be presented by Gordon Roberts of McGill University. In another, Robert Daasch of Portland State University will provide an introduction to statistics and test. He’ll specifically address outlier screening.
Is there a particular hot topic this year?
A topic that is hot this year is power-aware test. We got four panel proposals on that topic. [The selected panel, “Power-aware DFT¯Do We Really Need It?” will run from 5:00 p.m. to 6:30 p.m. Monday.] We also have two full sessions worth of papers on the topic.
We’ve also added another new feature to the conference this year—what we call “hot topic background” sessions. Power-aware test will be the focus of one such session. The background session [scheduled for 8:00 a.m. to 8:30 a.m. Wednesday] will take place in the same room as and right before the two sessions worth of papers on the topic.
What are the other hot topic background sessions?
There’s one more, “Overview of Test Generation and Analysis for Reducing Test Escapes,” on Thursday morning.
You mentioned the panel on power-aware test. What are other panel topics?
We have one very interesting panel, called the University DFT Tool Showdown. [It’s scheduled from 4:15 p.m. to 4:45 p.m. Wednesday.] Sun has made its OpenSPARC T1 and T2 processors available to universities, and during the workshop, four universities are going to demo their tools using these open-source commercially available processors. It will be interesting to see whether the universities can beat the industry in handling these real designs. A lot of university research is tried out on toy benchmark circuits, so there is always some skepticism about whether the results can really scale to industrial-sized circuits. Judges will evaluate these university tools and will give out a $2500 prize to the best one.
What’s the total panel lineup this year?
We have a total of six panels altogether. On Monday evening will be the one on power-aware DFT. Others, scheduled for Wednesday evening, include the university tool showdown as well as panels on analog test, test compression, debug war stories, and yield learning (see related post, "ITC panel to address yield learning: who pays, who gets the data").
There seems to be more emphasis on analog test this year.
Yes, what we found by looking at the attendee feedback was that there is a lot of interest in the mixed-signal and analog sessions, so we have good coverage this year.
What about board and system level test?
We are going to have some regular papers and sessions, and we’ve also got a lecture series on practical issues in board test. [It’s scheduled for 2:00 p.m. to 3:30 p.m. Wednesday.]
And in terms of system test—we are having a joint session with Autotestcon on DFT at the system level. Autotestcon’s attendee base is very different from ITC’s. It’s almost totally nonoverlapping, and we see a lot of benefits in joint sessions. [The Autotestcon joint session is scheduled for 2:00 p.m. to 3:30 p.m. Thursday.] What about workshops after the conference?
We have two workshops continuing from last year: ATE Vision 2020 and a workshop on defect- and data-driven testing. We also have one new workshop this year, which is on design for reliability and variability, which will address design and test innovations that can enabling chips to maintain acceptable reliability levels at reasonable cost.
For more information, visit www.itctestweek.org.
Power-aware test will be the focus of a panel discussion and two technical paper sessions and is a key topic at this year’s International Test Conference, says Nur Touba, Professor, Department of Electrical and Computer Engineering, University of Texas at Austin, and Program Chair of this year’s ITC. The conference and associated Test Week presentations, to be held October 26-31 in Santa Clara, CA, will also focus on other hot topics, Touba says, such as analog test, which will be addressed in an interactive talk with analog legend Bob Pease. Events of note include a new poster session, a panel on university DFT implementations and a new workshop on design for reliability and variability. Touba discussed this year’s ITC in a phone interview.
The theme of last year’s conference was “facing nanometer test challenges.” What’s this year’s theme?
The steering committee decided not to have a theme this year. The thinking was it really wasn’t driving the program a lot beyond possibly the selection of the keynote speaker.
Who is the keynote speaker this year?
Mike Lydon, VP of test and quality at Cisco, will deliver the keynote address, which is titled “Managing Test in the End-to-End, Mega Supply Chain.” He’s going to talk about managing the supply chain and using test to make real-time end-to-end adjustments over the product’s lifecycle.
Will you have invited addresses?
Yes, we have three invited talks. Just like last year, they will be after lunch each of the three days of the conference.
In the first one, “Computing at the Crossroads (and What Does it Mean to Verification and Test?),” Jan Rabaey of the University of California, Berkeley, will talk about how technology scaling, distributed computation, and physical models of computing will all have a profound effect on how we verify and test designs in the future.
The second talk—“Having FUN with Analog Test—will be given by Bob Pease, staff scientist at National Semiconductor and a legend in the analog community with 48 years of experience. He’s going to be having an interactive conversation—answering questions from the audience—which is something new for an ITC invited address.
Third talk will be given by Jeff Rearick, AMD Fellow, who will talk about how to tell if DFT and test are adding value to your company and how to justify your investment in test.
What are the program highlights this year?
We have added several new features to the program. One is a poster session, which differs from what some conferences do. Some conferences invite regular paper submissions that don’t make the cut to be presented as posters. What we’ve done is have a totally separate submission and review process for the posters. The thinking is, there are some people out there who have some really interesting data, but they don’t have time to write up a 10-page paper about it. The poster submissions require only a one-page summary, so it makes it easy for busy people to come and present their data.
Also, while the regular paper submission deadline was in February, the poster submission deadline was in July, which allows people to submit more late-breaking results. And by presenting a poster, they can get some feedback that helps them write a full paper for the next ITC. In addition, with the poster session we encouraged people to submit on nontraditional topics that wouldn’t necessarily be appropriate as research papers.
When is the poster session?
After the Wednesday afternoon panels last year we held a wine and cheese party. This year on Wednesday we are having an Oktoberfest party, and it’s during that party that the 27 posters will be presented. The presenters will have laptops available to show demos.
What about tutorials?
Another new feature we have this year is embedded tutorials. Of course we will have the 17 tutorials on Sunday and Monday, like we’ve had in the past, but the embedded tutorials will take place on Tuesday morning, during the conference itself. They are included with your registration—you don’t have to pay extra for them. One on mixed-signal production test will be presented by Gordon Roberts of McGill University. In another, Robert Daasch of Portland State University will provide an introduction to statistics and test. He’ll specifically address outlier screening.
Is there a particular hot topic this year?
A topic that is hot this year is power-aware test. We got four panel proposals on that topic. [The selected panel, “Power-aware DFT¯Do We Really Need It?” will run from 5:00 p.m. to 6:30 p.m. Monday.] We also have two full sessions worth of papers on the topic.
We’ve also added another new feature to the conference this year—what we call “hot topic background” sessions. Power-aware test will be the focus of one such session. The background session [scheduled for 8:00 a.m. to 8:30 a.m. Wednesday] will take place in the same room as and right before the two sessions worth of papers on the topic.
What are the other hot topic background sessions?
There’s one more, “Overview of Test Generation and Analysis for Reducing Test Escapes,” on Thursday morning.
You mentioned the panel on power-aware test. What are other panel topics?
We have one very interesting panel, called the University DFT Tool Showdown. [It’s scheduled from 4:15 p.m. to 4:45 p.m. Wednesday.] Sun has made its OpenSPARC T1 and T2 processors available to universities, and during the workshop, four universities are going to demo their tools using these open-source commercially available processors. It will be interesting to see whether the universities can beat the industry in handling these real designs. A lot of university research is tried out on toy benchmark circuits, so there is always some skepticism about whether the results can really scale to industrial-sized circuits. Judges will evaluate these university tools and will give out a $2500 prize to the best one.
What’s the total panel lineup this year?
We have a total of six panels altogether. On Monday evening will be the one on power-aware DFT. Others, scheduled for Wednesday evening, include the university tool showdown as well as panels on analog test, test compression, debug war stories, and yield learning (see related post, "ITC panel to address yield learning: who pays, who gets the data").
There seems to be more emphasis on analog test this year.
Yes, what we found by looking at the attendee feedback was that there is a lot of interest in the mixed-signal and analog sessions, so we have good coverage this year.
What about board and system level test?
We are going to have some regular papers and sessions, and we’ve also got a lecture series on practical issues in board test. [It’s scheduled for 2:00 p.m. to 3:30 p.m. Wednesday.]
And in terms of system test—we are having a joint session with Autotestcon on DFT at the system level. Autotestcon’s attendee base is very different from ITC’s. It’s almost totally nonoverlapping, and we see a lot of benefits in joint sessions. [The Autotestcon joint session is scheduled for 2:00 p.m. to 3:30 p.m. Thursday.] What about workshops after the conference?
We have two workshops continuing from last year: ATE Vision 2020 and a workshop on defect- and data-driven testing. We also have one new workshop this year, which is on design for reliability and variability, which will address design and test innovations that can enabling chips to maintain acceptable reliability levels at reasonable cost.
For more information, visit www.itctestweek.org.
针对雷达测试和UWB测试的信号源
编辑笔记：据国外媒体TMWORLD报道，R&S最新推出一款型号为AFQ100B的基带信号源产品。该产品可以与其AFQ-K264软件一起产生UWB测试信号。该产品可以用于各种UWB设备如接收机、I/Q调制器等。
The R&S AFQ100B baseband signal source from Rohde & Schwarz works with the company's R&S AFQ-K264 software to generate test signals for WiMedia UWB (ultrawideband) components such as receivers or I/Q modulators. With its 528-MHz bandwidth, the instrument also has the capability to handle aerospace and defense applications. In addition, Rohde & Schwarz offers options that permit the signal source to generate signals for other digital communications standards such as WCDMA, HSPA+, WiMAX, WLAN, and LTE.
For aerospace and defense applications, the R&S AFQ100B can deliver signals with modulated pulses or wide, nonlinear chirps for testing radar systems, according to the company. Pulse sequencer software permits users to configure pulsed signals, including any type of analog or digital modulation. Plug-ins for inserting classified contents into the pulses are also available.
To accommodate aerospace and defense companies that prefer to generate the required signals themselves, Rohde & Schwarz offers toolboxes that permit the transfer of those signals to the R&S AFQ100B. A removable hard disk enables manufacturers to keep confidential data secure.
http://www.rohde-schwarz.com/
The R&S AFQ100B baseband signal source from Rohde & Schwarz works with the company's R&S AFQ-K264 software to generate test signals for WiMedia UWB (ultrawideband) components such as receivers or I/Q modulators. With its 528-MHz bandwidth, the instrument also has the capability to handle aerospace and defense applications. In addition, Rohde & Schwarz offers options that permit the signal source to generate signals for other digital communications standards such as WCDMA, HSPA+, WiMAX, WLAN, and LTE.
For aerospace and defense applications, the R&S AFQ100B can deliver signals with modulated pulses or wide, nonlinear chirps for testing radar systems, according to the company. Pulse sequencer software permits users to configure pulsed signals, including any type of analog or digital modulation. Plug-ins for inserting classified contents into the pulses are also available.
To accommodate aerospace and defense companies that prefer to generate the required signals themselves, Rohde & Schwarz offers toolboxes that permit the transfer of those signals to the R&S AFQ100B. A removable hard disk enables manufacturers to keep confidential data secure.
http://www.rohde-schwarz.com/
NI推出业界速度最快的PXI嵌入式控制器和新型PXI系统配件
2008年10月，美国国家仪器有限公司（National Instruments，简称NI）于近日推出了业界速度最快的嵌入式控制器NI PXI-8108和两款新型的PXI系统配件，即 32GB的固态硬盘驱动器和NI PXI-8250系统监视模块。这些新产品提升了系统的性能和可靠度，在帮助工程师和科学家们获得更快的执行速度的同时有效减少测试时间，延长系统寿命。
PXI-8108嵌入式控制器，具有为高性能PXI和CompactPCI系统而设计的Intel Core 2 Duo T9400处理器。PXI-8108有着2.53GHz的双核处理器和800MHz的DDR2存储器，相比于上一代的双核产品NI PXI-8106，提升了25%的速度，而相比于上一代的单核产品NI PXI-8196，提供2倍的性能改进。使用NI LabVIEW 8.6软件，工程师和科学家们可以充分利用最新的双核控制器，如NI PXI-8108等，来简化多线程应用程序的开发，并且对现有LabVIEW代码无需做重大更改即可提升性能。PXI-8108还可以与NI LabVIEW Real-Time 和LabWindows™/CVI Real-Time Module软件配合使用，来实现灵活而持久的平台，用于确定性实时测量和控制。
“利用LabVIEW中的多核技术和最新的NI多核PXI嵌入式控制器，我们可以每周额外增加1个工作日的测试吞吐量，”Sanmina-SCI公司的制造测试工程师Alejandro Torres提到，“最重要的是，我们只需要简单地将原有的PXI单核嵌入式处理器升级到最新的NI PXI多核嵌入式控制器，对代码做很小修改，就可以实现吞吐量的提升。”
对于对系统要求具备最强性能和可靠度的工程师和科学家们，可以将NI PXI-8108控制器的标准旋转磁场式磁盘驱动器升级成32GB的PXI固态硬盘驱动器。配有32GB固态硬盘驱动器的PXI-8108可以提供0到55 oC的扩展工作温度范围，增加读写文件和流数据的速度和可靠性，同时由于没有移动的部件，在发生撞击和振动时提高持久性。而且，所有最新型的NI PXI和PXI Express Windows以及实时嵌入式控制器都可以升级成使用新型的32GB固态硬盘驱动器。
为了最大化PXI系统的效率和总寿命，NI公司现在提供了PXI-8250系统监视模块。工程师和科学家们可以利用这个模块进行编程，来监测系统的吸入和排出的温度、风扇速度、处理器和存储器使用情况、电源电压等。PXI-8250前面板上的LED显示了参数是否处在合适的工作范围内，前面板上的继电器可以连接到外部设备，如状态指示灯或警报等。
PXI-8108嵌入式控制器，具有为高性能PXI和CompactPCI系统而设计的Intel Core 2 Duo T9400处理器。PXI-8108有着2.53GHz的双核处理器和800MHz的DDR2存储器，相比于上一代的双核产品NI PXI-8106，提升了25%的速度，而相比于上一代的单核产品NI PXI-8196，提供2倍的性能改进。使用NI LabVIEW 8.6软件，工程师和科学家们可以充分利用最新的双核控制器，如NI PXI-8108等，来简化多线程应用程序的开发，并且对现有LabVIEW代码无需做重大更改即可提升性能。PXI-8108还可以与NI LabVIEW Real-Time 和LabWindows™/CVI Real-Time Module软件配合使用，来实现灵活而持久的平台，用于确定性实时测量和控制。
“利用LabVIEW中的多核技术和最新的NI多核PXI嵌入式控制器，我们可以每周额外增加1个工作日的测试吞吐量，”Sanmina-SCI公司的制造测试工程师Alejandro Torres提到，“最重要的是，我们只需要简单地将原有的PXI单核嵌入式处理器升级到最新的NI PXI多核嵌入式控制器，对代码做很小修改，就可以实现吞吐量的提升。”
对于对系统要求具备最强性能和可靠度的工程师和科学家们，可以将NI PXI-8108控制器的标准旋转磁场式磁盘驱动器升级成32GB的PXI固态硬盘驱动器。配有32GB固态硬盘驱动器的PXI-8108可以提供0到55 oC的扩展工作温度范围，增加读写文件和流数据的速度和可靠性，同时由于没有移动的部件，在发生撞击和振动时提高持久性。而且，所有最新型的NI PXI和PXI Express Windows以及实时嵌入式控制器都可以升级成使用新型的32GB固态硬盘驱动器。
为了最大化PXI系统的效率和总寿命，NI公司现在提供了PXI-8250系统监视模块。工程师和科学家们可以利用这个模块进行编程，来监测系统的吸入和排出的温度、风扇速度、处理器和存储器使用情况、电源电压等。PXI-8250前面板上的LED显示了参数是否处在合适的工作范围内，前面板上的继电器可以连接到外部设备，如状态指示灯或警报等。
NI拓宽智能相机系列产品选择
2008年9月——美国国家仪器有限公司（National Instruments，简称NI）近日推出3款最新智能相机产品，拓宽了其智能相机系列的产品线。NI 1744, NI 1762以及NI 1764三款产品具备更快的处理速度以及更高的图像分辨率，让工程师在嵌入式机器视觉应用中有了更多的选择。
在533 MHzPowerPC的工作环境中，NI 1744智能相机配有一个高分辨率的图像传感器，最多可采集130万像素（1280×1024）的图像。通过该产品，工业工程师和机器架构师可以检测产品的瑕疵。相比旧款智能相机，它具备了4倍的图像分辨率，确保了检测的精确性。
对于在模式匹配，OCR识别和条形码解读上有更高要求的工程师，NI 1762款智能相机同时提供了720 MHz 的TI DSP协处理器以及533 MHz PowerPC，在运行演算法时，相比旧款，速度提升了4倍。
新款NI 1764智能相机在所有新产品中具有最高的图像分辨率以及最优异的性能。它拥有130万图像传感器以及720MHz TI DSP协处理器。NI 1764对需要特大对象检测、精确定位及微小条形码识别等特性的高速工业线应用来说，不失为最佳选择。
新款智能相机产品同时包含NI Vision Builder for Automated Inspection (AI)产品，您无需编程即可在这款交互的环境下配置并发布完整的机器视觉应用。在直观的图像以及菜单驱动的软件下，工程师可以创建复杂的机器视觉应用，并和视觉算法以及基于状态的执行相合并，使用内置的状态图解编辑环行或分支运行。对于更高要求的应用，NI智能相机可以和LabVIEW软件和NI所有图像处理和机器视觉演算相集成。利用LabVIEW和Vision Builder AI软件同时支持所有智能相机的特性，工程师无需进行大更新，即可在2款软件的机器视觉应用中进行转换。
NI 智能相机系列的新产品扩宽了NI机器视觉产品的选择，并为机器视觉应用提供了范围更广的解决方案。
在533 MHzPowerPC的工作环境中，NI 1744智能相机配有一个高分辨率的图像传感器，最多可采集130万像素（1280×1024）的图像。通过该产品，工业工程师和机器架构师可以检测产品的瑕疵。相比旧款智能相机，它具备了4倍的图像分辨率，确保了检测的精确性。
对于在模式匹配，OCR识别和条形码解读上有更高要求的工程师，NI 1762款智能相机同时提供了720 MHz 的TI DSP协处理器以及533 MHz PowerPC，在运行演算法时，相比旧款，速度提升了4倍。
新款NI 1764智能相机在所有新产品中具有最高的图像分辨率以及最优异的性能。它拥有130万图像传感器以及720MHz TI DSP协处理器。NI 1764对需要特大对象检测、精确定位及微小条形码识别等特性的高速工业线应用来说，不失为最佳选择。
新款智能相机产品同时包含NI Vision Builder for Automated Inspection (AI)产品，您无需编程即可在这款交互的环境下配置并发布完整的机器视觉应用。在直观的图像以及菜单驱动的软件下，工程师可以创建复杂的机器视觉应用，并和视觉算法以及基于状态的执行相合并，使用内置的状态图解编辑环行或分支运行。对于更高要求的应用，NI智能相机可以和LabVIEW软件和NI所有图像处理和机器视觉演算相集成。利用LabVIEW和Vision Builder AI软件同时支持所有智能相机的特性，工程师无需进行大更新，即可在2款软件的机器视觉应用中进行转换。
NI 智能相机系列的新产品扩宽了NI机器视觉产品的选择，并为机器视觉应用提供了范围更广的解决方案。
从理论到实现，未来工程教育改革的趋势所向
2008年8月,美国国家仪器有限公司（National Instruments, 简称NI）近日在广州、大连两地成功举办第四届全国虚拟仪器技术教师交流会。本次交流会围绕“从理论到实现”这一主题展开，旨在为高校领域带来最先进的工程教育理念和技术，并且提供良好的平台帮助同领域的老师们增进彼此交流合作。来自全国24个省/直辖市108所高等院校的超过330位老师参与了此次活动，清华大学、上海交通大学等全国十多所工程类知名院校的共20多位教授专家分享了工程教育及科研方面的成果与心得。
大会以NI院校计划经理陈庆全先生和特邀嘉宾清华大学汽车工程系金振华博士的主题演讲拉开帷幕，向各位听众展望了未来工程教育的改革与发展趋势。其后的专题讲座中，来自全国重点高校的资深教授专家从测试测量、电子电路、信号处理、嵌入式系统等领域入手，帮助在座教师了解第一手参考资讯。交流会现场另特辟3个展示区域，其中最大的亮点即是NI在6月推出的采用高速USB即插即用连接的最新ELVIS II设计原型平台，其拥有12种精密仪器。它与电路仿真软件NI Multisim紧密结合，大大简化电路设计教学。另外，在配备各学科的课程资源的基础上，它还可以与Emmona、Quanser、Freescale等公司生产的配套电路板协同工作，帮助教师在实验室中教授通信、控制、微控制器和嵌入式设计等方面的知识。
实例展示配合前沿的技术讲座，让此次参会的老师们纷纷表示不虚此行，开拓了眼界和思路。如大连理工大学徐志祥老师所说：“交流会的内容非常充实，尤其是各校教学科研一线的老师介绍自己的体会，可以帮助我们少走弯路，更好地应用虚拟仪器技术为教学科研服务。”
作为教师交流会的延伸，NI于会后分别在华南理工大学和大连理工大学举办了针对教师的LabVIEW培训，为即将建立虚拟仪器实验室和教授LabVIEW课程的理工科教师们创造一个深入学习的机会。针对在校学生，NI也同期推出LabVIEW助理开发工程师认证（CLAD）院校优惠活动，旨在帮助高校学生成功学习LabVIEW，在就业选择上胜人一筹。
通过虚拟仪器教师交流会，NI旨在搭建一个平台汇聚更多院校老师、分享成功经验，并高效共享资源。这样的交流会和培训活动将在每年的暑期举办，NI将在不断提供最新的虚拟仪器技术产品的同时，结合教师交流会、教师培训以及多样的院校合作计划为中国的工程教育做出一份贡献。
NI 最新推出6.6GHz PXI Express射频矢量信号分析仪和矢量信号发生器
2008年8月,美国国家仪器有限公司（National Instruments，简称NI）近日推出了新型的射频矢量信号分析仪、射频矢量信号发生器和18插槽PXI Express机箱。在射频测量应用中，相比传统射频仪器，新产品将速度提升了近10倍。新型的软件定义型模块化仪器 ——NI PXIe-5663 6.6GHz射频矢量信号分析仪和NI PXIe-5673 6.6GHz射频矢量信号发生器，都将借助于NI PXIe-1075 18槽高带宽机箱发挥其性能。NI PXIe-5663能够以高达50MHz的瞬时带宽，对10MHz到6.6GHz的信号进行分析。而NI PXIe-5673则可以以高达100MHz的瞬时带宽，实现85MHz到6.6GHz的信号生成。NI PXIe-1075是业界中第一款每个插槽均使用1GB/s 专用带宽PCI Express通道的PXI Express机箱，总系统带宽更可高达4GB/s。
新型的射频模块化仪器充分利用了高性能多核处理器的优势，是高速射频和无线自动化测试应用的理想选择。在多核CPU上运行使用LabVIEW 8.6编写的并行化测量算法时，工程师们能够利用新型的射频矢量信号分析仪和射频矢量信号发生器，以比传统仪器更快的速度进行多种常用的射频测量。例如，射频模块化仪器能以快20多倍的速度进行单独的WCDMA测量。由于它可以在短短的8ms内，实现邻信道泄漏比 (ACLR) 等参数的测量，工程师们能够以5倍以上的速度改进，对WCDMA设备进行完整的定性分析。此外，工程师们还可以利用新型仪器更快地进行通用的测量。例如，使用NI PXIe-8106控制器以30kHz的分辨率带宽进行典型的50MHz频谱扫频，只需要4ms，而使用传统仪器进行相同的测量则需要100ms或者更多的时间。随着新型多核处理器的发布，基于PXI的射频测量所需时间会不断下降，而无需对射频仪器或NI LabVIEW编程进行改动，进而保证了测量性能的最大化、提高了系统寿命并降低了成本投资。
除了对性能的改进外，新型射频模块化仪器还基于完全软件定义的构架，提供了业界领先的测量灵活性。工程师们可以通过使用具体标准的LabVIEW工具包或编写专用的调制算法对软件进行简单的重新配置，就能实现开发和测试各种无线协议。NI公司及系统联盟商提供了用于许多现有和新兴的通信技术的LabVIEW工具包，包括WiMAX、GPS、WCDMA、GSM、EDGE、宽带视频广播、802.11、蓝牙、OFDM和MIMO。同时，工程师们可以将PXI射频仪器与高达1500种的模块进行集成，其中包括高速数字化仪、信号发生器和精密直流仪器等，来满足完整的测试需求。
新型的6.6GHz模块化仪器使用了最新的商业化技术，包括16位数模转换器和模数转换器来生成和数字化信号，用于实现优异的动态性能。NI PXIe-5673射频矢量信号发生器使用了直接射频上变频技术，提供了高达100MHz的射频带宽。使用额外的“缺陷模式”，工程师们可以使用板载的现场可编程门阵列 (FPGA) 芯片，快速手动调整增益不平衡、IQ偏置和正交偏斜。利用专为特定频率优化的基带缺陷模式，工程师们可以获得超过-85dBc的载波和镜频抑制。NI PXIe-5663射频矢量信号分析仪提供了通带平坦和低相位噪声特性，所以可以用于精确的测量调制信号。例如，在WCDMA中，2GHz时2600多个码元的典型EVM性能是0.8个百分点。另外，对于WiMAX而言，3.8GHz时的典型EVM性能是-52dB。
“现在，工程师们可以从基于LabVIEW和PXI平台的真正软件定义的射频仪器体验到性能的优越性，” NI公司射频与通信高级经理Joseph E. Kovacs先生表示，“借助于PXI Express的带宽和多核处理器的并行处理能力，NI软件定义的射频仪器将随着技术进步不断提升速度。我们的客户将不断受益于与传统仪器相比高达10被的速度提升以及更多核的处理器进入市场所带来的性能改进。”
NI PXI-1075 18插槽机箱提供了8个混合插槽供工程师们使用，可用于PXI Express设备或PXI混合插槽兼容的模块来最大限度地重用现有的PXI模块。为高性能系统设计的NI PXIe-1075，提供了0到50摄氏度的工作温度范围，而且还提供了集成的系统监视功能，包括电源管理及整个系统的风扇状态和温度监测等。
电容漏泄的测量
电容器是几乎所有电气设备上都会用到的主要器件。漏阻是电容器被测试的众多电气特征中的一个。漏阻通常被称为“IR”（Insulation Resistance，绝缘电阻），以“兆欧－微法”表示。在其它情况下，漏泄可能被表示为特定电压（通常为工作电压）下的漏泄电流。
电容器的漏泄是通过向电容施加一个固定电压，并测量产生的电流测得的。漏流将随时间呈指数衰减，因此在测量电流之前，施加电压必须达到一个已知的时间周期（保压时间）。
出于统计目的，必须测试一定数量的电容器来生成有用的数据。为了进行测试，就需要一套自动切换系统。
图 1所示为一套电容器漏泄测试系统，它采用了Keithley 6517A型静电计/源、7158型小电流扫描卡和C型开关卡，例如7111-S或7169A。插卡被安装在7002型开关主机中。
图 1，电容器漏泄测试系统
在该测试系统中，一组开关（7111-S型或7169A型）被用来向每个电容器施加测试电压。在常闭位置，电容器的一端被连接到电路LO。当开关触动时，电容器被连接到电压源。开关通常是交错触动的（例如，间隔2秒），从而在测量漏泄之前，每个电容器均可被充电相同的时间周期。若最大测试电压为110 V或更低，则可使用7111-S型开关卡；否则，则可使用7169A型开关卡测试高达500 V的电压。如果必须施加高于500 V的电压，则应该使用具有相应额定值的开关。
第二组开关（7158型）在经过合适的平稳时间后将每个电容器连接到皮安计。请注意，在电容器被切换至皮安计之前，它是被连接到电路LO的。这样就使得漏流在其充电器件亦可连续流通。
对于这种应用，单台仪器提供了电压源和小电流测量功能。6517A型可显示电阻或漏流，并可提供高达1000 VDC的电压，所以特别适合这一应用。
在测试过电容器之后，电压源应该被设置为零。有时候在将电容从测试夹具上拆除之前，必须使其放电。注意，图 1中的电容（C）通过继电器的常闭触点形成了放电通路。测试序列同步如下：
静态——7169A型继电器为常闭，7158型继电器为常闭。
施加电压（保压时间）——7169A型继电器连接至常开触点，7158型继电器仍然保持常闭。
测量电流——7169A型继电器仍保持在常开位置，7158型继电器连接至常开触点。
放电电容器——7169A型继电器连接至常闭触点，7158型继电器连接至常闭触点。
由于7169A型C型开关卡上的隔离开关在测量电流期间保持被激励状态，所有来自开关卡的任何偏移电流都与测量是无关的。
与电容器串联的电阻器（R）是本测试系统中的一个重要元件。它限制每个电容器的充电电流，并在电容器发生短路时保护继电器。此外，该电阻器还限制回馈安培表的交流增益。一般而言，当源电容增大时，噪声增益也会增大。该电阻器将增益限制为有限值。合理的限值是使RC时间常数为0.5～2秒。与静电计（pA）的HI端子串联的正偏二极管也起到限制交流增益的作用。
一个“同轴三柱－BNC”转换器（7078-TRX-BNC型）被用于将6517A连接到7158型开关卡。电容器通过低噪声同轴电缆连接到7158型开关卡。可使用绝缘线将7111-S开关卡连接到电容器。7169A型是通过接线头连接器进行连接。
奥组委使用NI LabVIEW 监测鸟巢健康状况
2008年7月，美国国家仪器有限公司（National Instruments，简称NI）近日宣布，负责国家防震减灾的政府机构——中国地震局 (CEA) 选择了CGM工程公司（美国国家仪器有限公司合作伙伴）开发的建筑健康监测（SHM）解决方案。该解决方案是基于NI LabVIEW图形化系统设计平台及NI CompactRIO可编程自动化控制器开发的系统，旨在帮助工程师们对新近建造的六座超大型建筑进行建筑健康监测。这六座标志性建筑包括了2008年北京夏季奥运会的2个主会场——北京国家体育场以及中国国家水上运动中心。
“该工程项目的主要目标是开发一个尖端的建筑健康监测解决方案。通过采用最新计算技术、传感器以及通信技术来实时监测建筑的稳定性、可靠性、可居住性等结构健康特性。” CGM工程公司副总裁Chris McDonald先生表示：“我们设计的系统能够采集建筑结构的振动信号，检测任何突发的结构特性变化，用以改善建筑结构，并有助于在发生地震、飓风、火灾等重大灾难时降低生命财产的损失。”
CGM 公司设计的9条64通道及2条36通道SHM系统中, 各包含多个CompactRIO控制器。它可以直接连接具备测量振动的加速度计以及实时机箱内同步的基于时间的GPS接收器。机箱内，LabVIEW FPGA模块可以保证每个测试通道的数据与GPS接收器上获得数据的误差保持在±10微秒内。LabVIEW实时模块同时用于编程实现用户可配置的滤波器来避免不必要噪声对低频测量造成的干扰。每个系统都密闭安装在坚固的NEMA标准机箱盒中，这可以方便设备在湿度高、温差变化大（-40°C to 70°C）的环境下进行操作。
SHM系统能够连续、实时地对每个区域进行监测，工程师可以在世界任何一地通过安全的因特网连接，远程接收当地存储的数据。不仅如此，当有任何意外情况发生时，工程师都可以采用独立或多元构架来配置系统，发送邮件通知。
中国地震局在众多方案中选择了基于NI技术的系统，正是因为NI具有连续且实时的监测、基于时间的GPS同步及在最低成本下实现最高通道数的优势。NI技术还能支持简单的开箱即用的安装模式及多种I/O选择，从而在系统需求更新时能够快速简便地完成重新配置。
除北京奥运会比赛场馆外，SHM系统也被应用于104层的上海世贸中心大楼、66层的北京柏悦酒店、240米的二滩混凝土拱坝、8,266米长的汕头斜拉桥以及具有隔震结构的北京中国地震局数据中心。最终，从该研究中所获得的数据将被用于提高未来楼宇的建筑整体性，减低灾难事故中人员的伤亡率。
NI LabVIEW 8.6 兼容多核、FPGA、无线等主流商业技术
2008年8月,美国国家仪器有限公司（National Instruments，简称NI）隆重发布了可应用于控制、测试及嵌入式系统开发的图形化系统设计平台的最新版本——LabVIEW 8.6。得益于LabVIEW软件平台天生并行的图形化编程方式，LabVIEW 8.6版本提供了全新工具帮助工程师和科学家们从多核处理器、现场可编程门阵列 (FPGAs) 及无线通信等商业技术中获益。
目前，为了能够使用这些最新技术，工程师们往往不得不使用非专为并行编程设计的软件工具。而最新版的LabVIEW则为他们提供了独立的平台，通过采用多核处理器技术提高测试及控制系统的吞吐量，在基于FPGA的高级控制及嵌入式原型应用中缩短开发时间，更便捷地创建分布式测量系统，采集远程数据。
“从机器人技术到混合动力汽车设计，为了满足前沿应用中的性能及效率需求，用户必须及时将诸如多核处理器、FPGA及无线通信等最新技术融入自己的应用，” NI公司总裁、CEO兼创始人之一James Truchard博士表示，“LabVIEW通过并行编程为上述技术的应用提供了捷径，同时它也为用户提供最大的灵活性来针对各种应用领域设计最优化的解决方案。”
多核处理器实现超级计算当标准系统越来越趋于引入多个处理核，测试测量系统实现大幅度性能提升的可能性也就越大。LabVIEW平台扩展了内嵌的多线程技术，在新版软件中通过多核优化特性提供超级计算性能，帮助工程师处理更大容量的测量数据，满足高级控制应用的要求，并提高测试系统的吞吐量。
为了提升性能，LabVIEW 8.6包含了超过1,200个重新优化的高级分析函数，在多核系统的控制测试应用中提供更快速、更强大的数学及信号处理功能。视觉应用同样能从多核系统中获益，NI视觉开发模块中创新性的图像处理函数，能够自动在多核间分配数据集。在全新的多核特性下，测试工程师通过新版LabVIEW的调制工具包开发测试无线设备的应用，其效率可提高4倍之多；控制系统工程师通过LabVIEW 8.6 控制设计及仿真模块实现并行模型仿真，效率可显著提高5倍之多。此外，使用LabVIEW框图自动布局功能，工程师们能够更便捷地识别代码的并行部分。
引入FPGA技术 – 无须专业级数字电路设计借助于LabVIEW直观的数据流模式，工程师们可以通过使用LabVIEW FPGA模块及基于FPGA的现成即用的商业硬件（如NI CompactRIO）来自定义测量及控制系统应用，如半导体验证及高级机器控制，从而实现更佳的性能。LabVIEW 8.6一如既往地将FPGA技术带给更多没有专业底层硬件描述语言或板级电路设计经验的工程师们。
LabVIEW 8.6进一步缩短了FPGA的开发时间，其新特性允许工程师们直接对CompactRIO可编程自动控制器 (PAC) 进行编程，而无须分别对FPGA编程。此外，全新仿真功能能够在电脑上验证FPGA应用，从而大大缩短了在编译上消耗的开发时间。LabVIEW 8.6还提供了全新IP开发及集成特性，包括全新快速傅立叶变换(FFT) IP核，实现频谱分析等功能，为机器状态监控及RF测试应用提供了更强的性能；全新的器件级IP(CLIP)节点，可便捷地将已有或第三方的IP导入LabVIEW FPGA，提升LabVIEW平台的开放性。
无线技术实现远程系统的数据采集及分析随着无线技术的发展，工程师们已经可以实现异地测量等应用。LabVIEW 8.6与无线技术的配合，能将数据采集应用扩展到新的领域中，如环境及建筑监测等。LabVIEW图形化编程的灵活性及无处不在的Wi-Fi网络构架能将无线连接融入全新或已有的基于PC的测量及控制系统中。
在最新无线数据采集设备及超过20家第三方无线传感器驱动的支持下，LabVIEW 8.6作为独立的软件平台，简化了分布式测量系统的编程过程。在LabVIEW 8.6中，无需作代码修改即可便捷地通过NI Wi-Fi 数据采集 (DAQ) 硬件来配置数据采集应用。同时，LabVIEW 8.6中全新的3-D可视化工具能够集成远程测量与设计模型，加速设计验证的整个过程。
通过任意网络驱动设备与LabVIEW应用进行交互当操作人员和系统间持续的连接与访问越来越普遍时，工程师希望可以在任一位置都能通过网络来与系统进行交互。LabVIEW 8.6允许将LabVIEW应用转化成电脑和实时硬件上的网络服务器（Web Service），从而能在任何网络驱动的设备上连接，如智能手机、PC机等。通过这一特性，工程师能够采用标准网络技术（如HTML、 JavaScript 及Flash）为LabVIEW应用开发远程用户界面。
目前，为了能够使用这些最新技术，工程师们往往不得不使用非专为并行编程设计的软件工具。而最新版的LabVIEW则为他们提供了独立的平台，通过采用多核处理器技术提高测试及控制系统的吞吐量，在基于FPGA的高级控制及嵌入式原型应用中缩短开发时间，更便捷地创建分布式测量系统，采集远程数据。
“从机器人技术到混合动力汽车设计，为了满足前沿应用中的性能及效率需求，用户必须及时将诸如多核处理器、FPGA及无线通信等最新技术融入自己的应用，” NI公司总裁、CEO兼创始人之一James Truchard博士表示，“LabVIEW通过并行编程为上述技术的应用提供了捷径，同时它也为用户提供最大的灵活性来针对各种应用领域设计最优化的解决方案。”
多核处理器实现超级计算当标准系统越来越趋于引入多个处理核，测试测量系统实现大幅度性能提升的可能性也就越大。LabVIEW平台扩展了内嵌的多线程技术，在新版软件中通过多核优化特性提供超级计算性能，帮助工程师处理更大容量的测量数据，满足高级控制应用的要求，并提高测试系统的吞吐量。
为了提升性能，LabVIEW 8.6包含了超过1,200个重新优化的高级分析函数，在多核系统的控制测试应用中提供更快速、更强大的数学及信号处理功能。视觉应用同样能从多核系统中获益，NI视觉开发模块中创新性的图像处理函数，能够自动在多核间分配数据集。在全新的多核特性下，测试工程师通过新版LabVIEW的调制工具包开发测试无线设备的应用，其效率可提高4倍之多；控制系统工程师通过LabVIEW 8.6 控制设计及仿真模块实现并行模型仿真，效率可显著提高5倍之多。此外，使用LabVIEW框图自动布局功能，工程师们能够更便捷地识别代码的并行部分。
引入FPGA技术 – 无须专业级数字电路设计借助于LabVIEW直观的数据流模式，工程师们可以通过使用LabVIEW FPGA模块及基于FPGA的现成即用的商业硬件（如NI CompactRIO）来自定义测量及控制系统应用，如半导体验证及高级机器控制，从而实现更佳的性能。LabVIEW 8.6一如既往地将FPGA技术带给更多没有专业底层硬件描述语言或板级电路设计经验的工程师们。
LabVIEW 8.6进一步缩短了FPGA的开发时间，其新特性允许工程师们直接对CompactRIO可编程自动控制器 (PAC) 进行编程，而无须分别对FPGA编程。此外，全新仿真功能能够在电脑上验证FPGA应用，从而大大缩短了在编译上消耗的开发时间。LabVIEW 8.6还提供了全新IP开发及集成特性，包括全新快速傅立叶变换(FFT) IP核，实现频谱分析等功能，为机器状态监控及RF测试应用提供了更强的性能；全新的器件级IP(CLIP)节点，可便捷地将已有或第三方的IP导入LabVIEW FPGA，提升LabVIEW平台的开放性。
无线技术实现远程系统的数据采集及分析随着无线技术的发展，工程师们已经可以实现异地测量等应用。LabVIEW 8.6与无线技术的配合，能将数据采集应用扩展到新的领域中，如环境及建筑监测等。LabVIEW图形化编程的灵活性及无处不在的Wi-Fi网络构架能将无线连接融入全新或已有的基于PC的测量及控制系统中。
在最新无线数据采集设备及超过20家第三方无线传感器驱动的支持下，LabVIEW 8.6作为独立的软件平台，简化了分布式测量系统的编程过程。在LabVIEW 8.6中，无需作代码修改即可便捷地通过NI Wi-Fi 数据采集 (DAQ) 硬件来配置数据采集应用。同时，LabVIEW 8.6中全新的3-D可视化工具能够集成远程测量与设计模型，加速设计验证的整个过程。
通过任意网络驱动设备与LabVIEW应用进行交互当操作人员和系统间持续的连接与访问越来越普遍时，工程师希望可以在任一位置都能通过网络来与系统进行交互。LabVIEW 8.6允许将LabVIEW应用转化成电脑和实时硬件上的网络服务器（Web Service），从而能在任何网络驱动的设备上连接，如智能手机、PC机等。通过这一特性，工程师能够采用标准网络技术（如HTML、 JavaScript 及Flash）为LabVIEW应用开发远程用户界面。
NI针对高带宽测量推出最新1 GHz带宽的PXI量化仪
2008年8月，美国国家仪器有限公司（National Instruments，简称NI）近日推出NI PXI-5154量化仪/基于PC的示波器，大大增加了拥有20多个高端、高精度和高通道数的相关产品种类。具备双通道的1 GHz PXI-5154量化仪可提供高达2 GS/s的实时采样率（对于重复信号，可达20 GS/s的等时采样率），满足了高速、接近纳秒速率的信号采集。此外，该量化仪配有该类产品中最大的板载内存——每通道存储可高达250 MB, 并同时可以在拓展的数据采集窗口上提供稳定的高采样率。新产品非常适合在消费电子、半导体、航空/国防和生命科学等行业的自动化测试与数据流中的应用。
利用NI T-Clock专利技术，工程师们可以实现PXI量化仪与各种NI硬件的集成，其中包括任意波形发生器和数字波形发生器/分析仪，以自定义并构建一个完整的自动化混合信号测试系统。利用T-Clock技术，工程师们还可以实现多个PXI-5154量化仪的同步，从而在单个PXI底板上搭建高达34通道的系统，系统的所有通道可进行1GS/s的同步采样，并且模块间达到皮秒（百亿分之一秒）级的同步精度。此量化仪的高带宽性能和多模块间的同步功能，特别适合于质谱、雷达、信号情报、无创测试和高通道数物理学试验等应用。
工程师们更可以将新量化仪与NI LabVIEW Signal Expres软件相结合，快速采集数据、执行测量并察看和分析Microsoft Excel中的数据。此外，PXI-5154量化仪支持所有的NI软件，包括LabVIEW和LabWindowsTM/CVI，以及ANSI、Microsoft C++和Visual Basic等其他开发环境。
DDRI/II/III 参数及协议和XDR 参数测量
简介：随着DDR向更高密度、更小体积方向发展，对DDR探头连接带来了挑战，DDR信号检测甚至存在信号反射风险和其他信号完整性问题。本演讲稿将与你分享安捷伦新型的DDR BGA探头适配器如何解决探测难点；以及DDR协议验证、参数测量、XDR参数等难点的解决。
点击此处下载PDF全文第一部分
点击此处下载PDF全文第二部分
点击此处下载PDF全文第一部分
点击此处下载PDF全文第二部分
NI最新推出针对LabVIEW软件的高性能、确定性的以太网硬件产品
2008年10月，美国国家仪器有限公司（National Instruments，简称NI）近日推出新款高性能的8槽机箱，它可以将确定性的拓展I/O传输到NI LabVIEW图形化开发平台。新型机箱针对诸如分布式控制、机器制造和硬件在环控制，可以提供高速、低振动的通信性能。
新型NI9144 8槽扩展机箱可以与超过30种C系列的模拟和数字模块兼容，不仅可以获得高精度的测量质量，同时能够直接与大量的传感器进行互联。这种扩展机箱与具有2个以太网接口的NI 实时控制器协同工作（包括NI CompactRIO和PXI）。NI 9144自身也具备2个以太网网接口，这使得工程师能够以菊花链的形式，通过控制器进行多个NI 9144的互连，从而实现在最低处理器资源占用的情况下，不但保持了系统确定性，同时扩展了实时应用系统。NI 9144通过标准的5类以太网电缆进行连接，通过使用系统同步时钟，能够实现在相距100米的2个机箱间进行通信。新型机箱专为工业应用而设计，拥有从-40 -70摄氏度宽温工作范围和50g的抗震等级。
由于LabVIEW 8.6实时模块可以自动辨识所有连接的从属硬件和模块，NI 9144可以在经过最简单的配置后直接正常工作。通过拖曳式I/O变量、即时测试面板和I/O强制配合，LabVIEW提供了简单的快速访问物理通道和进行故障排除的方法。
新型确定性的以太网机箱是一款整合了诸如FPGA的LabVIEW图形化编程开发软件、工业通信硬件和模块化仪器技术的最新产品，这使得它成为了机器制造、大型分布式系统、大型物理和硬件在环应用的理想选择。
订阅：
博文 (Atom)
